UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 499
UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(7) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error during reception must be set within the allowable error range using the
As shown in Figure 12-10, the receive data latch timing is determined by the counter set using the UAnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit)
can be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
Remark
FL = (Brate)
Minimum allowable transfer rate: FLmin = 11 × FL −
transfer rate
transfer rate
transfer rate
Maximum
Brate: UARTAn baud rate (n = 0, 1)
k:
FL:
Latch timing margin: 2 clocks
allowable
allowable
Minimum
UARTAn
following equation.
n = 0, 1
Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0, 1)
1-bit data length
−
1
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Figure 12-10. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
Bit 0
Bit 0
FL
Bit 0
User’s Manual U17716EJ2V0UD
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
FLmin
k − 2
2k
FLmax
× FL =
Bit 7
Bit 7
Bit 7
21k + 2
Parity bit
2k
Parity bit
Parity bit
FL
Stop bit
Stop bit
Stop bit
497
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