UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 344
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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342
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an
overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect
processing is shown below.
The following problem may occur when a long pulse width is measured in the free-running timer mode.
<1> Read the TQ0CCRa register (setting of the default value of the TIQ0a pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TQ0CCRa register.
Remark
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may
not be obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or
use software. An example of how to use software is shown below.
TQ0CCRa register
INTTQ0OV signal
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
(incorrect).
Actually, the pulse width must be (20000H + D
TIQ0a pin input
16-bit counter
TQ0OVF bit
Example of incorrect processing when capture trigger interval is long
a = 0 to 3
TQ0CE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U17716EJ2V0UD
D
a0
<1> <2>
a1
− D
1 cycle of 16-bit counter
a0
) because an overflow occurs twice.
Pulse width
D
a0
<3> <4>
D
a1
D
a1
a1
− D
a0
)
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