UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 328

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

326
• Compare operation
When the TQnCE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the
TOQ00 to TOQ03 and TOQ10 pins are inverted. When the count value of the 16-bit counter later matches the
set value of the TQnCCRa register, a compare match interrupt request signal (INTTQnCCa) is generated, and
the output signals of the TOQ00 to TOQ03 and TOQ10 pins are inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Confirm that the overflow flag is
set to 1 and then clear it to 0 by executing the CLR instruction via software.
The TQnCCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
at that time by anytime write, and compared with the count value.
Remark
INTTQnCC0 signal
INTTQnCC1 signal
INTTQnCC2 signal
INTTQnCC3 signal
TQnCCR0 register
TQnCCR1 register
TQnCCR2 register
TQnCCR3 register
TOQn0 pin output
TOQ01 pin output
TOQ02 pin output
TOQ03 pin output
INTTQnOV signal
16-bit counter
Figure 7-35. Basic Timing in Free-Running Timer Mode (Compare Function)
TQnOVF bit
TQnCE bit
n = 0, 1
a = 0 to 3
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
D
10
10
D
20
D
30
User’s Manual U17716EJ2V0UD
D
00
D
20
Cleared to 0 by
CLR instruction
D
D
30
D
00
11
D
20
D
30
D
00
CLR instruction
Cleared to 0 by
D
11
D
11
D
21
D
31
D
D
01
21
D
31
CLR instruction
Cleared to 0 by
D
01
D
11
D
21
D
31
D
01