UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 435

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• Total number of A/D conversion clocks
Software trigger
Hardware
trigger
(2) A/D converter n mode register 1 (ADAnM1)
Notes 1. When two or more channels are scanned (ADAnS register ≠ 00H)
Cautions 1. See Table 11-2 Number of Conversion Clocks for the ADAnFR1 and ADAnFR0 bits.
ADAnFR1 ADAnFR0
Trigger Mode
The ADAnM1 register is an 8-bit register that specifies the number of conversion clocks.
The number of conversion clocks includes the number of sampling clocks.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
0
1
1
2. The stabilization time of the number of stabilized clocks elapses after the ADAnCE bit is set from 0 to 1.
Timer
trigger
External
trigger
2. When ADAnM0.ADAnCE bit = 1 (conversion enabled), changing the ADAnFR1 and
3. Be sure to clear bits 2 to 7 to “0”.
If the trigger is input during this time, the trigger is acknowledged after the lapse of the stabilization time.
As a result, the maximum total number of A/D conversion clocks is the above stabilization time plus the
number of stabilized clocks.
(n = 0, 1)
ADAnM1
ADAnFR0 bits is prohibited.
0
1
0
1
After reset: 00H
Continuous select
Continuous scan
One-shot select
One-shot scan
Continuous select/
one-shot select
Continuous scan/
one-shot scan
Continuous select/
one-shot select
Continuous scan/
one-shot scan
Setting prohibited
62 (3.10
93 (4.65
124 (6.20
Number of Conversion Clocks
Operation Mode
0
(f
μ
μ
XX
s)
s)
μ
s)
= 20 MHz)
Table 11-2. Number of Conversion Clocks
CHAPTER 11 A/D CONVERTERS 0 AND 1
R/W
1 buffer
4 buffers
1 buffer
1 buffer
4 buffers
1 buffer
1 buffer
4 buffers
1 buffer
1 buffer
4 buffers
1 buffer
0
Address: ADA0M1 FFFFF201H, ADA1M1 FFFFF221H
User’s Manual U17716EJ2V0UD
Number of stabilized clocks +
number of trigger acknowledgment
clocks + number of conversion
clocks
Number of trigger acknowledgment
clocks + number of conversion
clocks
Noise elimination time + number of
trigger acknowledgment clocks +
number of conversion clocks
0
Total Number of A/D Conversion
Clocks by First Trigger After
Setting ADAnCE Bit = 1
Note 2
33
50
54
Number of Stabilized Clocks
0
(f
XX
= 20 MHz)
0
−
Note 2
0
Number of conversion clocks
Number of conversion clocks
Number of conversion clocks
Number of conversion clocks
Number of conversion clocks
Number of conversion clocks
Number of conversion clocks
Total Number of A/D Conversion Clocks
− (Conversion end with one conversion)
− (Conversion end with one conversion)
− (Conversion end with one conversion)
by Second or Subsequent Trigger After
ADAnFR1 ADAnFR0
Number of Trigger Acknowledge
6
7
8
Setting ADAnCE Bit = 1
Clocks (f
XX
−
= 20 MHz)
Note 1
Note 1
Note 1
433