UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 600
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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598
(c) Internal RAM data status register (RAMS)
The RAMS register is a flag register that indicates whether the internal RAM is valid or not. The RAMS register
is a special register. It can be written only by a combination of specific sequences (see 3.4.7 Special
registers).
For the RAMS register, see (5) RAM retention voltage detection operation.
This register can be read or written in 8-bit or 1-bit units.
This register is set to 01H by RESET pin input (during RAM access only) and watchdog timer overflow. The
value is retained when reset by other factors.
Cautions 1. When writing to the RAMS register, use command register PRCMD2.
RAMS
After reset: 01H
Note This register is set to 01H by RESET pin input (during RAM access only) and watchdog timer
2. The following shows the specific sequence after reset.
overflow. The value is retained when reset by other factors.
• Setting conditions: Detection of voltage lower than specified level (2.0 V ± 0.1 V)
• Clearing condition: Writing of 0 in specific sequence
RAMF
7
0
0
1
Note
Valid
Invalid
R/W
6
0
CHAPTER 16 RESET FUNCTIONS
Address: FFFFF892H
Writing 1 via a specific sequence
Generation of reset signal by watchdog timer overflow
RESET pin input while RAM is being accessed
User’s Manual U17716EJ2V0UD
5
0
Internal RAM data valid/invalid
4
0
3
0
2
0
1
0
RAMF
<0>
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