UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 286
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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284
(f) TMQ0 capture/compare registers 1 to 3 (TQ0CCR1 to TQ0CCR3)
The TQ0CCR1 to TQ0CCR3 registers are not used in the external event count mode. However, the set
values of the TQ0CCR1 to TQ0CCR3 registers are transferred to the CCR1 to CCR3 buffer registers.
When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers,
compare match interrupt request signals (INTTQ0CC1 to INTTQ0CC3) are generated.
When the TQ0CCR1 to TQ0CCR3 registers are not used, it is recommended to set their values to
FFFFH.
TQ0CCIC3.TQ0CCMK3).
Caution Set the TQ0IOC0 register to 00H.
Remark
Figure 7-17. Register Setting for Operation in External Event Count Mode (2/2)
TMQ0 I/O control register 1 (TQ0IOC1) and TMQ0 option register 0 (TQ0OPT0) are not used
in the external event count mode.
Also mask the registers by the interrupt mask flags (TQ0CCIC1.TQ0CCMK1 to
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U17716EJ2V0UD
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