UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 419

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4.6
to generate the A/D conversion start trigger signal (TQTADT00, TQTADT01) of A/D converters 0 and 1.
TQ1OPT3.TQ1AT13 bits.
ORed and output. Therefore, two or more trigger sources can be specified at the same time.
culled interrupt signals.
(TQ1OPT1.TQ1ICE, TQ1OPT1.TQ1IOE bits), the A/D conversion start trigger is not output.
trigger signal depending on the status of the count-up/count-down of the 16-bit counter, if so set by the TQ1AT02,
TQ1AT03, TQ1AT12, and TQ1AT13 bits.
The V850ES/IE2 has a function to select four trigger sources (INTTQ1OV, INTTQ1CC0, INTTP1CC0, INTTP1CC1)
The trigger sources are specified by the TQ1OPT2.TQ1AT00 to TQ1OPT2.TQ1AT03 and TQ1OPT3.TQ1AT10 to
• TQ1AT00, TQ1AT10 bits = 1:
• TQ1AT01, TQ1AT11 bits = 1:
• TQ1AT02, TQ1AT12 bits = 1:
• TQ1AT03, TQ1AT13 bits = 1:
The A/D conversion start trigger signals selected by the TQ1AT00 to TQ1AT03 and TQ1AT10 to TQ1AT13 bits are
The INTTQ1OV and INTTQ1CC0 signals selected by the TQ1AT00, TQ1AT01, TQ1AT10, and TQ1AT11 bits are
Therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled
The trigger sources (INTTP1CC0 and INTTP1CC1) from TMP1 have a function to mask the A/D conversion start
• TQ1ATM02, TQ1ATM12 bits:
• TQ1ATM03, TQ1ATM13 bits:
• TQ1ATM02, TQ1ATM12 bits = 0
• TQ1ATM02, TQ1ATM12 bits = 1
• TQ1ATM03, TQ1ATM13 bits = 0
• TQ1ATM03, TQ1ATM13 bits = 1
A/D conversion start trigger signal generated when INTTQ1OV (counter underflow) occurs.
A/D conversion start trigger signal generated when INTTQ1CC0 (cycle match) occurs.
A/D conversion start trigger signal generated when INTTP1CC0 (match of TP1CCR0 register of TMP1 during
tuning operation) occurs.
A/D conversion start trigger signal generated when INTTP1CC1 (match of TP1CCR1 register of TMP1 during
tuning operation) occurs.
Correspond to the TQ1AT02 and TQ1AT12 bits and control INTTP1CC0 (match interrupt signal) of TMP1.
Correspond to the TQ1AT03 and TQ1AT13 bits and control INTTP1CC1 (match interrupt signal) of TMP1.
A/D conversion start trigger output function
The A/D conversion start trigger signal is output when the 16-bit counter counts up (TQ1OPT0.TQ1CUF bit =
0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down
(TQ1OPT0.TQ1CUF bit = 1).
The A/D conversion start trigger signal is output when the 16-bit counter counts down (TQ1OPT0.TQ1CUF
bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts up
(TQ1OPT0.TQ1CUF bit = 0).
The A/D conversion start trigger signal is output when the 16-bit counter counts up (TQ1OPT0.TQ1CUF bit =
0), and the A/D conversion start trigger signal is not output when the 16-bit counter counts down
(TQ1OPT0.TQ1CUF bit = 1).
The A/D conversion start trigger signal is output when the 16-bit counter counts down (TQ1OPT0.TQ1CUF
bit = 1), and the A/D conversion start trigger signal is not output when the 16-bit counter counts up
(TQ1OPT0.TQ1CUF bit = 0).
CHAPTER 9 MOTOR CONTROL FUNCTION
User’s Manual U17716EJ2V0UD
417