UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 62

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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The operating conditions of the PRERR flag are shown below. For the operating conditions of the PRERR2
flag, read PRCMD and SYS as PRCMD2 and SYS2 in the following explanation.
(i) Set condition (PRERR flag = 1)
Remark
(ii) Clear condition (PRERR flag = 0)
Cautions 1. If 0 is written to the PRERR bit of the SYS register which is not a special register,
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When data is written to a special register without writing anything to the PRCMD register (when <3> is
executed without executing <2> in 3.4.7 (1) Setting data to special registers)
When data is written to an on-chip peripheral I/O register other than a special register (including
execution of a bit manipulation instruction) after writing data to the PRCMD register (if <3> in 3.4.7 (1)
Setting data to special registers is not the setting of a special register)
When 0 is written to the PRERR flag
When the system is reset
2. If data is written to the PRCMD register, which is not a special register, immediately after
Even if an on-chip peripheral I/O register is read (excluding execution of a bit manipulation
instruction) between a write access to the PRCMD register and a write access to a special register
(such as an access to the internal RAM), the PRERR flag is not set and data can be written to the
special register.
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0 (the
write access takes precedence).
a write access to the PRCMD register, the PRERR bit is set to 1.
CHAPTER 3 CPU FUNCTION
User’s Manual U17716EJ2V0UD