UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 348

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
later detected, the count value of the 16-bit counter is stored in the TQ0CCRa register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTQ0CCa) is generated.
interrupt request signal (INTTQ0OV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TQ0OPT0.TQ0OVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
346
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0a pin is
The pulse width is calculated as follows.
If the valid edge is not input to the TIQ0m pin even when the 16-bit counter counted up to FFFFH, an overflow
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × Number of times for which TQ0OVF bit is set to 1 + Captured value) × Count clock cycle
INTTQ0CCa signal
TQ0CCRa register
INTTQ0OV signal
Remark
TIQ0a pin input
a = 0 to 3
16-bit counter
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
a = 0 to 3
Figure 7-41. Basic Timing in Pulse Width Measurement Mode
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0000H
User’s Manual U17716EJ2V0UD
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
D
3