UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 592
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.1 Overview
16.2 Registers to Check Reset Source
590
The following reset functions are available.
• Reset by RESET pin input
• Reset by watchdog timer overflow (WDTRES)
• System reset by low-voltage detector (LVI) (LVIRES)
• System reset by power-on-clear circuit (POC) (POCRES)
(1) Reset source flag register (RESF)
Note The value of this register is cleared to 00H after a reset by RESET pin input or the power-on-clear circuit
Cautions 1. Only “0” can be written to each bit of this register. If writing “0” conflicts with setting the
The RESF register is a special register that can be written only by a combination of specific sequences (see
3.4.7 Special registers).
The RESF register indicates that a reset signal is generated by the watchdog timer (WDT).
The LVIRF and WDT2RF bits are cleared by reset via the RESET pin or by a bit manipulation instruction or
store instruction (writing 0 to the LVIRF and WDT2RF bits).
This register is read or written in 8-bit units. However, bit 0 is write-only.
This register is cleared to 00H by RESET pin input and reset by the power-on-clear circuit (POC). The default
value differs if the source of reset is other than these.
(POC). When a reset is executed by watchdog timer overflow, this register is set to 10H or 11H. When
reset by the low-voltage detector (LVI), bit 4 retains the value before reset and bit 0 is undefined.
2. When writing to the RESF register, use command register PRCMD.
RESF
After reset: 00H
flag (occurrence of reset), setting the flag takes precedence.
WDT2RF
LVIRF
0
1
0
1
0
Note
Not generated/cleared
Generated
Cleared
Write disabled
CHAPTER 16 RESET FUNCTIONS
R/W
0
User’s Manual U17716EJ2V0UD
Address: FFFFF888H
0
Clear of RESF2.LVIRFS bit
Reset signal from WDT
WDT2RF
0
0
0
LVIRF
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