UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 156
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 6-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
(a) Function as compare register
(b) Function as capture register (TP0CCR1 and TP2CCR1 registers only)
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Notes 1. TMP0 and TMP2 only
Remark
The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1.
The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the
16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTPnCC1) is generated. If TOPm1 pin output is enabled at this time, the output of the TOPm1 pin is
inverted (the TOP11 pin is not provided in the V850ES/IE2).
The compare register is not cleared by the TPnCTL0.TPnCE bit = 0.
Remark
When the TPkCCR1 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TPkCCR1 register if the valid edge of the capture trigger input pin
(TIPk1 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is
stored in the TPkCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIPk1 pin) is detected.
Even if the capture operation and reading the TPkCCR1 register conflict, the correct value of the TPkCCR1
register can be read.
The capture register is cleared by the TPkCTL0.TPkCE bit = 0.
Remark
2. TMP0 and TMP2 only (also TMP3 in software trigger mode)
3. TMP0, TMP2, and TMP3 only
4. Writing to the TPnCCR1 register is the trigger.
Operation Mode
Note 3
For anytime write and batch write, see 6.6 (2) Anytime write and batch write.
m = 0, 2, 3
k = 0, 2
Note 2
Note 1
Note 1
Note 2
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
User’s Manual U17716EJ2V0UD
Capture/Compare Register
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
How to Write Compare Register
Note 4
Note 4
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