UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 415
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Write signal of
request signal
(4) Rewriting TQ1OPT0.TQ1CMS bit
<1> If the TQ1CCR1 register is rewritten when the TQ1CMS bit is 0, the transfer request signal is set.
<2> The register is not transferred because the TQ1CMS bit is set to 1 and the transfer request signal is
<3> The transfer request signal is not set even if the TQ1CCR1 register is written when the TQ1CMS bit is 1.
<4> The transfer request signal is not set even if the TQ1CCR1 register is written when the TQ1CMS bit is 1,
<5> The transfer request signal is set if the TQ1CCR1 register is written when the TQ1CMS bit is 0.
<6> Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not
CCR1 buffer
TQ1CMS bit
TQ1CCR1
TQ1CCR1
Transfer
Transfer
The TQ1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten during
timer operation (when TQ1CTL0.TQ1CE bit = 1). However, the operation and caution illustrated in Figure 9-31
are necessary.
If the TQ1CCR1 register is written when the TQ1CMS bit is cleared to 0, a transfer request signal (internal
signal) is set.
When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer
request signal is cleared. This transfer request signal is also cleared when the TQ1CMS bit is set to 1.
counter
register
register
If the TQ1CMS bit is set to 1 in this status, the transfer request signal is cleared.
cleared.
so even if the TQ1CMS bit is cleared to 0, transfer does not occur at the subsequent transfer timing.
Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared.
performed at the next transfer timing.
timing
16-bit
0000H
i
CHAPTER 9 MOTOR CONTROL FUNCTION
Figure 9-36. Rewriting TQ1CMS Bit
i
User’s Manual U17716EJ2V0UD
Clear
<1>
<2>
k
<3>
<4>
r
r
Clear
<5>
s
s
<6>
413
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