UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 578
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UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) Generation of exception in servicing program
Servicing program of maskable interrupt or exception
The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt
request signal (0 is the highest priority), but it can be set as desired via software. The priority order is set using
the xxPRn0 to xxPRn2 bits of the interrupt control request register (xxlCn), provided for each maskable
interrupt request signal. After system reset, an interrupt request signal is masked by the xxMKn bit and the
priority order is set to level 7 by the xxPRn0 to xxPRn2 bits.
The priority order of maskable interrupts is as follows.
Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the
servicing of the higher priority interrupt has been completed and the RETI instruction has been executed.
A pending interrupt request signal is acknowledged after the current interrupt servicing has been completed
and the RETI instruction has been executed.
Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed),
Remark
• EIPC saved to memory or register
• EIPSW saved to memory or register
• TRAP instruction
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
(High)
maskable interrupts are suspended and not acknowledged.
xx: Identification name of each peripheral unit (see Table 14-2)
n: Peripheral unit number (see Table 14-2)
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Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7
CHAPTER 14 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U17716EJ2V0UD
← Exception such as TRAP instruction acknowledged.
(Low)
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