UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 342

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UPD70F3714GC-8BS-A

Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3714GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
340
Note The TQ0OVF0 and TQ0OVF1 flags are set on the internal RAM by software.
<1> Read the TQ0CCR0 register (setting of the default value of the TIQ00 pin input).
<2> Read the TQ0CCR1 register (setting of the default value of the TIQ01 pin input).
<3> An overflow occurs.
<4> Read the TQ0CCR0 register.
<5> Read the TQ0CCR1 register.
<6> Same as <3>
TQ0CCR0 register
TQ0CCR1 register
INTTQ0OV signal
TQ0OVF0 flag
TQ0OVF1 flag
servicing, and clear the overflow flag to 0.
Read the TQ0OVF0 flag. If the TQ0OVF0 flag is 1, clear it to 0.
Because the TQ0OVF0 flag is 1, the pulse width can be calculated by (10000H + D
Read the TQ0OVF1 flag. If the TQ0OVF1 flag is 1, clear it to 0 (the TQ0OVF0 flag is cleared in
<4>, and the TQ0OVF1 flag remains 1).
Because the TQ0OVF1 flag is 1, the pulse width can be calculated by (10000H + D
(correct).
TIQ00 pin input
TIQ01 pin input
16-bit counter
Example when two capture registers are used (using overflow interrupt)
TQ0OVF bit
TQ0CE bit
FFFFH
0000H
Note
Note
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Set the TQ0OVF0 and TQ0OVF1 flags to 1 in the overflow interrupt
D
00
User’s Manual U17716EJ2V0UD
<1>
D
10
<2>
D
00
<3>
D
D
01
10
<4>
D
11
<5> <6>
D
01
D
11
01
− D
00
11
).
− D
10
(1/2)
)

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