UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 219
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3714GC-8BS-A
Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet
1.UPD70F3713GC-8BS-A.pdf
(674 pages)
Specifications of UPD70F3714GC-8BS-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 219 of 674
- Download datasheet (7Mb)
• Capture operation
When the TPkCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPka pin is
detected, the count value of the 16-bit counter is stored in the TPkCCRa register, and a capture interrupt request
signal (INTTPkCCa) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTPkOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TPkOPT0.TPkOVF bit) is also set to 1. Confirm that the overflow flag is
set to 1 and then clear it to 0 by executing the CLR instruction via software.
Remark
INTTPkCC0 signal
INTTPkCC1 signal
TPkCCR0 register
TPkCCR1 register
INTTPkOV signal
TIPk0 pin input
TIPk1 pin input
16-bit counter
Figure 6-37. Basic Timing in Free-Running Timer Mode (Capture Function)
TPkOVF bit
TPkCE bit
k = 0, 2
FFFFH
0000H
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U17716EJ2V0UD
D
00
D
CLR instruction
Cleared to 0 by
10
D
00
D
D
01
10
D
11
CLR instruction
Cleared to 0 by
D
D
01
02
D
11
D
12
CLR instruction
Cleared to 0 by
D
02
D
D
03
12
D
13
D
03
D
13
217
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