UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 519

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UPD70F3714GC-8BS-A

Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3714GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
INTCB0R signal
(2) Operation timing
CB0TSF bit
SCKB0 pin
SOB0 pin
(1) Write 07H to the CB0CTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CB0CTL2 register, and set the transfer data length to 8 bits.
(3) Write C1H to the CB0CTL0 register, and select the transmission mode and MSB first at the same time
(4) The CB0STR.CB0TSF bit is set to 1 by writing the transmit data to the CB0TX register, and the device
(5) When a serial clock is input, output the transmit data from the SOB0 pin in synchronization with the
(6) When transmission of the transfer data length set with the CB0CTL2 register is completed, stop the
(7) To continue transmission, write the transmit data to the CB0TX register again after the INTCB0R signal
(8) To end transmission, write the CB0CTL0.CB0PWR bit = 0 and the CB0CTL0.CB0TXE bit = 0.
external clock (SCKB0), and slave mode.
as enabling the operation of the communication clock (f
waits for a serial clock input.
serial clock.
serial clock output and transmit data output, generate the reception end interrupt request signal
(INTCB0R) at the last edge of the serial clock, and clear the CB0TSF bit to 0.
is generated, and wait for a serial clock input.
(1)
(2)
(3)
(4)
(5)
Bit 7
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
Bit 6
Bit 5 Bit 4
Bit 3 Bit 2
User’s Manual U17716EJ2V0UD
Bit 1
(6)
Bit 0
(7)
CCLK
Bit 7
).
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(8)
CCLK
) =
517

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