UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 440

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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11.4 Operation
11.4.1 Basic operation
438
Caution A/D converters 0 and 1 are capable of simultaneous sampling of two circuits.
A/D conversion is executed by the following procedure.
(1) Select an analog input pin, operation mode, and trigger mode, by using the ADAnM0, ADAnM1, ADAnM2, and
(2) In the software trigger mode, setting the ADAnM0.ADAnCE bit to 1 starts A/D conversion after the lapse of the
(3) When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
(4) When sampling has been performed for a specific time, the sample & hold circuit enters the hold status, and
(5) Set bit 9 of the successive approximation register (SAR). The tap selector changes the level of the voltage tap
(6) The voltage generated by the voltage tap of the array is compared with the analog input voltage by a
(7) Next, bit 8 of the successive approximation register (SAR) is automatically set, and the next comparison is
ADAnS registers
is enabled is determined by the specification of the ADAnM1.ADAnFR0 and ADAnM1.ADAnFR1 bits.
Note If the ADAnM0, ADAnM2 and ADAnS registers are written during A/D conversion, or if a valid trigger is
number of stabilized clocks (n = 0, 1). If the ADAnCE bit is set to 1 in the hardware trigger mode (external
trigger mode, timer trigger mode), the A/D converter enters the trigger standby status. For details, see 11.3 (2)
A/D converter n mode register 1 (ADAnM1).
sample & hold circuit.
holds the input analog voltage until A/D conversion ends.
of the array to the reference voltage (1/2AV
comparator. If the analog input voltage is found to be greater than the reference voltage (1/2AV
result of comparison, the most significant bit (MSB) of the successive approximation register (SAR) remains
set. If the analog input voltage is less than the reference voltage (1/2AV
started. The voltage tap of the array is selected according to the value of bit 9, to which the result has been
already set.
The voltage tap of the array and the analog input voltage are compared and bit 8 of the SAR is manipulated
according to the result of the comparison.
Comparison is continued like this to bit 0 of the SAR.
Bit 9 = 0: (1/4AV
Bit 9 = 1: (3/4AV
Analog input voltage ≥ Voltage tap of array: Bit 8 = 1
Analog input voltage ≤ Voltage tap of array: Bit 8 = 0
input, the conversion result is not correctly stored in the ADAnCRm register (m = 0 to 3) and the
conversion operation before the change is initialized and performed from the beginning again.
Note
(n = 0, 1). The setting of the number of stabilized clocks immediately after A/D conversion
REFn
REFn
)
)
CHAPTER 11 A/D CONVERTERS 0 AND 1
User’s Manual U17716EJ2V0UD
REFn
).
REFn
), the MSB of the SAR is reset.
REFn
) as a