UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 507

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(a) How to use CB0SCE bit
(i) In single reception mode
(ii) In continuous reception mode
<1> When the reception of the last data is completed with INTCB0R interrupt servicing, clear the
<2> When the reception is disabled after the reception of the last data has been completed, check
<1> Clear the CB0SCE bit to 0 during reception of the last data with INTCB0R interrupt servicing by
<2> After receiving the INTCB0R signal of the last reception, read the last data from the CB0RX
<3> When the reception is disabled after the reception of the last data has been completed, check
CB0SCE bit to 0, and then read the CB0RX register.
that the CB0STR.CB0TSF bit is 0, and then clear the CB0PWR and CB0RXE bits to 0. To
continue reception, set the CB0SCE bit to 1 and start the next receive operation by performing a
dummy read of the CB0RX register.
the reception before the last reception, and then read the CB0RX register.
register.
that the CB0STR.CB0TSF bit is 0, and then clear the CB0PWR and CB0RXE bits to 0. To
continue reception, set the CB0SCE bit to 1 and start the next receive operation by performing a
dummy read of the CB0RX register.
Caution In continuous reception mode, the serial clock is not stopped until the
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
reception executed when the CB0SCE bit is cleared to 0 is completed after the
reception is started by a dummy read.
User’s Manual U17716EJ2V0UD
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