UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 416

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4.5
as a slave. The conversion start trigger signal of A/D converters 0 and 1 can be set as the A/D conversion start trigger
source by the INTTP1CC0 and INTTP1CC1 signals of TMP1 and the INTTQ1OV and INTTQ1CC0 signals of TMQ1.
414
This section explains the tuning operation of TMP1 and TMQ1 in the 6-phase PWM output mode.
In the 6-phase PWM output mode, the tuning operation is performed with TMQ1 serving as the master and TMP1
(1) Tuning operation starting procedure
The TMP1 and TMQ1 registers should be set using the following procedure to perform the tuning operation.
(a) Setting of TMP1 register (stop the operations of TMQ1 and TMP1 (by clearing the TQ1CTL0.TQ1CE
(b) Setting of TMQ1 register
(c) Setting of TMQOP1 (TMQ1 option) register
(d) Setting of alternate function
(e) Set the TP1CE bit to 1 and set the TQ1CE bit to 1 immediately after that to start the 6-phase PWM
TMP1 tuning operation for A/D conversion start trigger signal output
bit and TP1CTL0.TP1CE bit to 0))
• Set the TP1CTL1 register to 85H (set the tuning operation slave mode and free-running timer mode).
• Clear the TP1OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TP1CCR0 and TP1CCR1 registers (set the default value for comparison
• Set the TQ1CTL1 register to 07H (set the master mode and 6-phase PWM output mode).
• Set an appropriate value to the TQ1IOC0 register (set the output mode of TOQ1T1 to TOQ1T3).
• Clear the TQ1OPT0 register to 00H (select the compare register).
• Set an appropriate value to the TQ1CCR0 to TQ1CCR3 registers (set the default value for comparison
• Set the TQ1CTL0 register to 0xH (clear the TQ1CE bit to 0 and set the operating clock of TMQ1).
• Set an appropriate value to the TQ1OPT1 and TQ1OPT2 registers.
• Set an appropriate value to the TQ1IOC3 register (set TOQ1B1 to TOQ1B3 in the output mode).
• Set an appropriate value to the TQ1DTC register (set the default value for comparison for starting the
• Set the alternate function to the port by setting the port control mode.
output operation
Rewriting the TQ1CTL0, TQ1CTL1, TP1CTL0, and TP1CTL1 registers is prohibited during operation. The
operation and the PWM output waveform are not guaranteed if any of these registers is rewritten during
operation.
(reading/writing) the other TMQ1, TMP1, and TMQ1 option registers is prohibited until the
TP1CTL0.TP1CE bit is set to 1 and then the TQ1CE bit is set to 1.
for starting the operation).
However, clear the TQ1OL0 bit to 0 and set the TQ1OE0 bit to 1 (enable positive phase output). Unless
this setting is made, the crest interrupt (INTTQ1CC0) and valley interrupt (INTT010V) do not occur.
Consequently, the conversion start trigger signal of A/D converters 0 and 1 is not correctly generated.
for starting the operation).
The operating clock of TMQ1 set by the TQ1CTL0 register is also supplied to TMP1, and the count
operation is performed at the same timing. The operating clock of TMP1 set by the TP1CTL0 register is
ignored.
operation).
However, rewriting the TQ1CTL0.TQ1CE bit to clear it is permitted.
CHAPTER 9 MOTOR CONTROL FUNCTION
User’s Manual U17716EJ2V0UD
Manipulating