UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 484

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4 Interrupt Request Signals
reception end interrupt request signal and transmission enable interrupt request signal follow in this order.
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The following three interrupt request signals are generated from UARTAn.
• Reception error interrupt request signal (INTUAnRE)
• Reception end interrupt request signal (INTUAnR)
• Transmission enable interrupt request signal (INTUAnT)
Among these three interrupt signals, the reception error interrupt signal has the highest default priority, and the
(1) Reception error interrupt request signal (INTUAnRE)
(2) Reception end interrupt request signal (INTUAnR)
(3) Transmission enable interrupt request signal (INTUAnT)
A reception error interrupt request signal is generated while reception is enabled by ORing the three types of
reception errors (parity error, framing error, and overrun error) explained in the UAnSTR register section.
A reception end interrupt request signal is output when data is shifted into the UARTAn receive shift register
and transferred to the UAnRX register in the reception enabled status.
No reception end interrupt request signal is generated in the reception disabled status.
If transmit data is transferred from the UAnTX register to the UARTAn transmit shift register with transmission
enabled, the transmission enable interrupt request signal is generated.
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Table 12-2. Interrupts and Their Default Priorities
Reception error
Reception end
Transmission enable
Interrupt
User’s Manual U17716EJ2V0UD
Priority
High
Low