UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 136

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

134
(3) When releasing STOP mode by interrupt request
PLL output clock
STOP status
OST counter
<1> When the STOP mode is set, both the oscillator and PLL stop.
<2> When the STOP mode is released, the oscillator is activated and the OST counter starts counting the
<3> When half the oscillation stabilization time set to the OSTS has elapsed, PLL starts operating. The
<4> After half the oscillation stabilization time has elapsed, the lockup wait time starts. The remaining
<5> When the lockup time of PLL is over, clock supply to the internal circuitry is started. At this time, the
<6> The operation to be performed when the STOP mode is released by RESET input or LVIRES or
At this time, PLL is stopped in the STOP mode. The OST counter is initialized.
oscillation stabilization time. At this time, PLL remains stopped.
clock generated by the oscillator must be stabilized before PLL starts operating.
oscillation stabilization time is “1/2 the oscillation stabilization time”. Take this into consideration
when setting a value to the OSTS register.
count time of the OST counter is the lockup wait time.
status before the STOP mode was set is recovered.
POCRES signal generation is the same as that in (1) Power on (power-on reset) and (2) Reset
input with power on.
V
f
CPU
X1
DD
H
00H (initialization)
In STOP
mode
<1>
CHAPTER 5 CLOCK GENERATOR
STOP mode released
is 1/2 of set value of
User’s Manual U17716EJ2V0UD
clock from oscillator
stabilization time of
OSTS register
Oscillation
<2>
<3>
PLL lockup time is
1/2 of set value of
OSTS register
<4>
Status before STOP mode was
set is resumed after release of
STOP mode
<5> <6>
PLL output stabilized
00H
The actual