UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 135

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Reset input with power on
CPU reset signal
Note RESET pin input, or WDTRES, LVIRES, or POCRES signal generation
Cautions 1. After the reset signal is released, a specific wait time (oscillation stabilization time)
PLL output clock
OST counter
<1> PLL stops during the reset period and the oscillation stabilization time set using the OSTS register.
<2> When the oscillation stabilization time that elapses after the reset signal is released expires, PLL stop
<3> PLL is locked when counting of the lockup time is over. The OST counter is initialized to 00H.
<4> When the lockup time expires, the CPU releases the reset signal and operates in the clock-through
Reset
is released, and counting the lockup time starts.
mode (f
2. To avoid malfunction due to noise, do not change the division ratio of the CPU operation
f
V
Note
CPU
X1
DD
elapses.
clock (f
division ratio, be sure to select the PLL mode.
H
X
). The CPU operation clock (f
CPU
00H (initialization)
) by using the PCC register before setting the PLL mode. Before changing the
<1>
CHAPTER 5 CLOCK GENERATOR
Oscillation stabilization time
Oscillation stabilization
of clock from oscillator
User’s Manual U17716EJ2V0UD
13.1 ms (2.5 MHz)
CPU
time
) is f
XX
/8. The PLL mode can be set by software.
13.1 ms (2.5 MHz)
PLL lockup time
<2>
f
XX
mode after RESET
/8 of clock-through
PLL output stabilized
<3>
00H
<4>
133