UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 36

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UPD70F3714GC-8BS-A

Manufacturer Part Number
UPD70F3714GC-8BS-A
Description
MCU 32BIT V850ES/LX2 64-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Ix2r
Datasheet

Specifications of UPD70F3714GC-8BS-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, UART/USART
Peripherals
LVD, PWM, WDT
Number Of I /o
39
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3714GC-8BS-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
34
(2) NMI status saving registers (FEPC, FEPSW)
(3) Interrupt source register (ECR)
FEPSW
31 to 16
15 to 0
Bit position
FEPC
There are two NMI status saving registers, FEPC and FEPSW.
Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to
FEPC and the contents of the program status word (PSW) are saved to FEPSW.
The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is
saved to FEPC, except for some instructions.
The current PSW contents are saved to FEPSW.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
When the RETI instruction has been executed, the values of FEPC and FEPSW are restored to the PC and
PSW, respectively.
Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an
interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This
register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
ECR
31
31
0
0
31
FECC
EICC
Bit name
0
0
0 0 0 0
0 0 0 0
26 25
Non-maskable interrupt (NMI) exception code
Exception, maskable interrupt exception code
0
FECC
0
0 0 0 0
CHAPTER 3 CPU FUNCTION
User’s Manual U17716EJ2V0UD
0
0
0 0 0 0
(PC contents saved)
16 15
0
0
Description
0 0 0 0
EICC
8
(PSW contents saved)
7
0
0
0
(x: Undefined)
(x: Undefined)
000000xxH
00000000H
0xxxxxxxH
After reset
After reset
After reset

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