UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 534

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

532
INTCB0T signal
(2) Operation timing
CB0TSF bit
SCKB0 pin
SOB0 pin
(1) Write 07H to the CB0CTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CB0CTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CB0CTL0 register, and select the transmission mode, MSB first, and continuous
(4) The CB0STR.CB0TSF bit is set to 1 by writing the transmit data to the CB0TX register, and the device
(5) When a serial clock is input, output the transmit data from the SOB0 pin in synchronization with the
(6) When transfer of the transmit data from the CB0TX register to the shift register is completed and
(7) To continue transmission, write the transmit data to the CB0TX register again after the INTCB0T signal
(8) When a serial clock is input following completion of the transmission of the transfer data length set with
(9) When transfer of the transmit data from the CB0TX register to the shift register is completed and
(10) When the clock of the transfer data length set with the CB0CTL2 register is input without writing to the
(11) To release the transmission enable status, write the CB0CTL0.CB0PWR bit = 0 and the
Caution In continuous transmission mode, the reception end interrupt request signal (INTCB0R) is
external clock (SCKB0), and slave mode.
transfer mode at the same time as enabling the operation of the communication clock (f
waits for a serial clock input.
serial clock.
writing to the CB0TX register is enabled, the transmission enable interrupt request signal (INTCB0T) is
generated.
is generated.
the CB0CTL2 register, continuous transmission is started.
writing to the CB0TX register is enabled, the INTCB0T signal is generated.
transmission with the current transmission, do not write to the CB0TX register.
CB0TX register, clear the CB0TSF bit to 0 to end transmission.
CB0CTL0.CB0TXE bit = 0 after checking that the CB0TSF bit = 0.
(1)
(2)
(3)
not generated.
(4)
(5)
Bit 7
CHAPTER 13 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
(6)
Bit 6
Bit 5
Bit 4 Bit 3
(7)
User’s Manual U17716EJ2V0UD
Bit 2
Bit 1
Bit 0
(8)
Bit 7
(9)
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
(10)
Bit 0
To end continuous
CCLK
(11)
).
CCLK
) =