UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 494

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6 Dedicated Baud Rate Generator
and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated
baud rate generator output can be selected for each channel.
492
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter,
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
(a) Base clock
(b) Serial clock generation
Caution If the CPU clock (f
Remarks 1. n = 0, 1
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to
UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (f
the UAnPWR bit = 0, f
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register.
The base clock (f
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.
f
f
XX
XX
f
f
f
XX
XX
XX
f
f
f
/1024
/2048
XX
XX
XX
2. f
f
f
f
/128
/256
/512
XX
XX
XX
/16
/32
/64
f
XX
/2
/4
/8
XX
UAnCKS3 to UAnCKS0
: Peripheral clock frequency
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UCLK
UAnPWR bit
UAnCTL1:
Selector
Figure 12-9. Configuration of Baud Rate Generator
) is selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
UCLK
CPU
is fixed to the low level.
) is slower than f
f
UCLK
User’s Manual U17716EJ2V0UD
UAnPWR, UAnTXE bit (or UAnRXE bit)
UAnBRS7 to UAnBRS0
Match detector
8-bit counter
UCLK
UAnCTL2:
, UARTAn cannot be used.
1/2
Baud rate
UCLK
). When