UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 454

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(2) 4-buffer mode (software trigger continuous select: 4 buffers)
Remark
(1) The ADA0CE bit = 1 (enable)
(2) The ANI02 pin is A/D converted
(3) The conversion result is stored in the ADA0CR0 register (9) The conversion result is stored in the ADA0CR3 register
(4) The ANI02 pin is A/D converted
(5) The conversion result is stored in the ADA0CR1 register (11) Return to (2)
(6) The ANI02 pin is A/D converted
Figure 11-11. Example of 4-Buffer Mode Operation (Software Trigger Continuous Select: 4 Buffers)
In this mode, the voltage of one analog input pin (ANInm) is A/D converted four times and the results are
stored in the ADAnCRm register.
When the 4th A/D conversion ends, an A/Dn conversion end interrupt request signal (INTADn) is generated.
After the end of A/D conversion, the conversion is started again from the beginning, unless the
ADAnM0.ADAnCE bit is cleared to 0. It is not necessary to set (1) the ADAnM0.ADAnCE bit to restart A/D
conversion
Note In the software trigger continuous select 4-buffer mode, the A/D conversion operation is not stopped
This mode is suitable for applications in which the average of the A/D conversion results of one analog input
pin is calculated.
Remark
ANInm
ANInm
ANInm
ANInm
Analog Input Pin
ADA0M0
This is an operation example with the following setting.
ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 00, ADA0M0.ADA0TMD bit = 0,
ADA0M2.ADA0BS bit = 1, ADA0S.ADA0S1 and ADA0S.ADA0S0 bits = 10
unless the ADAnM0.ADAnCE bit is cleared to 0. If the ADAnCRm register is not read before the next
A/D conversion ends, it is overwritten.
n = 0, 1
m = 0 to 3
Note
.
ADAnCR0
ADAnCR1
ADAnCR2
ADAnCR3
A/D Conversion Result Register
ANI00
ANI01
ANI02
ANI03
CHAPTER 11 A/D CONVERTERS 0 AND 1
(×4)
User’s Manual U17716EJ2V0UD
(7) The conversion result is stored in the ADA0CR2 register
(8) The ANI02 pin is A/D converted
(10) The INTAD0 interrupt request signal is generated
(12) To end the conversion, the ADA0CE bit = 0 (stop)
A/D converter 0
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3