UPD70F3714GC-8BS-A Renesas Electronics America, UPD70F3714GC-8BS-A Datasheet - Page 14

• Manufacturer Part Number: UPD70F3714GC-8BS-A
• Description: MCU 32BIT V850ES/LX2 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Ix2r

Specifications of UPD70F3714GC-8BS-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, UART/USART
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 15 STANDBY FUNCTION .................................................................................................. 579
CHAPTER 16 RESET FUNCTIONS ..................................................................................................... 590
12
14.3 Maskable Interrupts ............................................................................................................... 552
14.4 External Interrupt Request Input Pins (INTP0 to INTP6) .................................................... 566
14.5 Software Exception ................................................................................................................ 568
14.6 Exception Trap ....................................................................................................................... 571
14.7 Multiple Interrupt Servicing Control..................................................................................... 575
14.8 Interrupt Response Time of CPU.......................................................................................... 577
14.9 Periods in Which CPU Does Not Acknowledge Interrupts ................................................ 578
14.10 Caution .................................................................................................................................... 578
15.1 Overview ................................................................................................................................. 579
15.2 Control Registers ................................................................................................................... 581
15.3 HALT Mode ............................................................................................................................. 583
15.4 IDLE Mode............................................................................................................................... 585
15.5 STOP Mode ............................................................................................................................. 587
15.6 Securing Oscillation Stabilization Time............................................................................... 589
16.1 Overview ................................................................................................................................. 590
16.2 Registers to Check Reset Source ........................................................................................ 590
16.3 Operation ................................................................................................................................ 592
14.2.2 Restore .......................................................................................................................................550
14.2.3 Non-maskable interrupt status flag (NP) .....................................................................................551
14.3.1 Operation ....................................................................................................................................552
14.3.2 Restore .......................................................................................................................................554
14.3.3 Priorities of maskable interrupts..................................................................................................555
14.3.4 Interrupt control registers (xxICn) ...............................................................................................559
14.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)...........................................................................562
14.3.6 In-service priority register (ISPR) ................................................................................................564
14.3.7 Maskable interrupt status flag (ID) ..............................................................................................565
14.4.1 Noise elimination.........................................................................................................................566
14.4.2 Edge detection............................................................................................................................567
14.5.1 Operation ....................................................................................................................................568
14.5.2 Restore .......................................................................................................................................569
14.5.3 Exception status flag (EP)...........................................................................................................570
14.6.1 Illegal opcode definition ..............................................................................................................571
14.6.2 Debug trap ..................................................................................................................................573
15.3.1 Setting and operation status .......................................................................................................583
15.3.2 Releasing HALT mode................................................................................................................583
15.4.1 Setting and operation status .......................................................................................................585
15.4.2 Releasing IDLE mode .................................................................................................................585
15.5.1 Setting and operation status .......................................................................................................587
15.5.2 Releasing STOP mode ...............................................................................................................587
16.3.1 Reset operation via RESET pin ..................................................................................................592
16.3.2 Reset operation by watchdog timer (WDT) overflow (WDTRES) ................................................594
16.3.3 Low-voltage detector (LVI)..........................................................................................................595
16.3.4 Power-on-clear circuit (POC) ......................................................................................................603
User’s Manual U17716EJ2V0UD