R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 11

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 BXOR ........ Bit exclusive OR ......................... Bit Manipulation Instruction ... 106
6.3.11 CLIPS ........ CLIP as Signed ............................ Arithmetic Instruction ............. 108
6.3.12 CLIPU ........ CLIP as Unsigned ........................ Arithmetic Instruction ............. 111
6.3.13 DIVS .......... DIVide as Signed ........................ Arithmetic Instruction ............. 113
6.3.14 DIVU ......... DIVide as Unsigned .................... Arithmetic Instruction ............. 114
6.3.15 FMOV ........ Floating-point MOVe .................. Floating-Point Instruction........ 115
6.3.16 JSR/N ......... Jump to SubRoutine with No delay slot
6.3.17 LDBANK ... LoaD register BANK .................. System Control Instruction...... 121
6.3.18 LDC ........... LoaD to Control register ............. System Control Instruction...... 123
6.3.19 MOV .......... MOVe structure data ................... Data Transfer Instruction......... 124
6.3.20 MOV .......... MOVe reverse stack .................... Data Transfer Instruction......... 127
6.3.21 MOVI20 .... MOVe Immediate 20bits data ..... Data Transfer Instruction......... 130
6.3.22 MOVI20S .. MOVe Immediate 20bits data and 8bits Shift left
6.3.23 MOVML.L MOVe Multi-register Lower part Data Transfer Instruction......... 133
6.3.24 MOVMU.L MOVe Multi-register Upper part Data Transfer Instruction......... 136
6.3.25 MOVRT ..... MOVe Reverse Tbit .................... Data Transfer Instruction......... 139
6.3.26 MOVU ....... MOVe structure data as Unsigned
6.3.27 MULR ........ MULtiply to Register .................. Arithmetic Instruction ............. 142
6.3.28 NOTT ........ NOT Tbit ..................................... Data Transfer Instruction......... 143
6.3.29 PREF .......... PREFetch data to cache ............... Data Transfer Instruction......... 144
6.3.30 RESBANK REStore from registerBANK ...... System Control Instruction...... 145
6.3.31 RTS/N ........ ReTurn from Subroutine with No delay slot
6.3.32 RTV/N ....... ReTurn to Value and from subroutine with No delay slot
6.3.33 SHAD ........ SHift Arithmetic Dynamically .... Shift Instruction ....................... 150
6.3.34 SHLD ......... SHift Logical Dynamically ......... Shift Instruction ....................... 152
6.3.35 STBANK ... STore register BANK .................. System Control Instruction...... 154
6.3.36 STC ............ STore Control register ................. System Control Instruction...... 156
SH-2E CPU Instructions................................................................................................... 157
6.4.1
6.4.2
BLD ........... Bit LoaD ...................................... Bit Manipulation Instruction ... 94
BLDNOT ... Bit LoaDNOT .............................. Bit Manipulation Instruction ... 96
BOR ........... Bit OR ......................................... Bit Manipulation Instruction ... 98
BORNOT ... Bit ORNOT ................................. Bit Manipulation Instruction ... 100
BSET ......... Bit SET ........................................ Bit Manipulation Instruction ... 102
BST ............ Bit STore ..................................... Bit Manipulation Instruction ... 104
ADD .......... ADD Binary ................................ Arithmetic Instruction ............. 157
ADDC ........ ADD with Carry .......................... Arithmetic Instruction ............. 158
...................................................... Branch Instruction ................... 118
...................................................... Data Transfer Instruction......... 131
...................................................... Data Transfer Instruction......... 140
...................................................... Branch Instruction ................... 147
...................................................... Branch Instruction ................... 148
Rev. 3.00 Jul 08, 2005 page ix of xiv