R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 44

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Exception Handling
3.7.2
When a TRAPA instruction is executed, trap instruction exception handling is started. The CPU
operates as follows.
1. The start address of the exception service routine corresponding to the vector number specified
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the start address of the
4. Execution jumps to the address fetched from the exception handling vector table and program
3.7.3
An instruction located immediately after a delayed branch instruction is said to be located in the
delay slot. If the instruction in the delay slot is undefined code, slot illegal instruction exception
handling is started when that undefined code is decoded. Also, if the instruction in the delay slot
is one that modifies the program counter (PC), slot illegal instruction exception handling is started
when that instruction is decoded. Moreover, in the case of a product that does not have an FPU, or
if the FPU is in the module standby state, a floating-point instruction or FPU-related instruction is
treated as undefined code, and if located in a delay slot, will cause slot illegal instruction exception
handling to be started when decoded. In addition, if the product that does not have a register bank,
register bank-related instructions are treated as undefined code. If located in a delay slot, when
decoded they will cause slot illegal instruction handling to be started.
Furthermore, if an instruction located in a delay slot is a 32-bit instruction, RESBANK instruction,
DIVS instruction, or DIVU instruction, slot illegal instruction exception handling will be started
when this instruction is decoded.
CPU operations in slot illegal instruction exception handling are as follows.
1. The start address of the exception service routine is fetched from the exception handling vector
2. The status register (SR) is saved on the stack.
3. The program counter (PC) is saved on the stack. The saved PC value is the jump destination
4. Execution jumps to the address fetched from the exception handling vector table and program
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by the TRAPA instruction is fetched from the exception handling vector table.
instruction following the TRAPA instruction.
execution commences. The jump is not a delayed branch.
table.
address of the delayed branch instruction immediately preceding an undefined code,
instruction that overwrites the PC, 32-bit instruction, RESBANK instruction, DIVS
instruction, or DIVU instruction.
execution commences. The jump is not a delayed branch.
Trap Instruction
Slot Illegal Instructions