R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 287

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.66
Format
TST
TST
TST.B #imm,
Description
Logically ANDs the contents of general registers Rn and Rm, and sets the T bit to 1 if the result is
0 or clears the T bit to 0 if the result is not 0. The Rn data does not change. The contents of general
register R0 can also be ANDed with zero-extended 8-bit immediate data, or the contents of 8-bit
memory accessed by indirect indexed GBR addressing can be ANDed with 8-bit immediate data.
The R0 and memory data do not change.
Operation
TST(long m,long n)
{
}
TSTI(long i) /* TEST #imm,R0 */
{
}
TSTM(long i) /* TST.B #imm,@(R0,GBR) */
if ((R[n]&R[m])==0) T=1;
else T=0;
PC+=2;
long temp;
temp=R[0]&(0x000000FF & (long)i);
if (temp==0) T=1;
else T=0;
PC+=2;
Rm,Rn
#imm,R0
@(R0,GBR)
TST
AND Operation
T Bit Setting
Abstract
Rn & Rm, when result is 0, 1 → T
R0 & imm, when result is 0, 1 → T
(R0 + GBR) & imm, when result is
0, 1 → T
/* TST Rm,Rn */
TeST logical
Rev. 3.00 Jul 08, 2005 page 271 of 484
Code
0010nnnnmmmm1000 1
11001000iiiiiiii 1
11001100iiiiiiii 3
Section 6 Instruction Descriptions
Logical Instruction
REJ09B0051-0300
Cycle T Bit
Test
results
Test
results
Test
results