R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 392

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Part Number:
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Manufacturer:
Renesas Electronics America
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Section 8 Pipeline Operation
Double-
precision
floating-
point
instructions
Rev. 3.00 Jul 08, 2005 page 376 of 484
REJ09B0051-0300
Type
Floating-
point
register-
register
transfer
instructions
Floating-
point
register-
immediate
instructions
Floating-
point
register
load
instructions
Floating-
point
register
store
instructions
Category
of Stages
Number
6
5
6
5
Execution
States
2
1
2
2
0/2/3/4 *
1/2/3/4 *
0/2/3/4 *
Latency
1/0 *
1
4
0
0
3
4
4
4
• These instruc-
• These instruc-
• These instruc-
• This is 32-bit
• This instruction
• These instruc-
• This is 32-bit
• This instruction
tions use the
FPU load/store
pipeline.
tions use the
FPU arithmetic
operation
pipeline.
tions use the
FPU load/store
pipeline and
memory access
pipeline.
instruction.
uses the FPU
load/store
pipeline and
memory access
pipeline.
tions use the
FPU load/store
pipeline and
memory access
pipeline.
instruction.
uses the FPU
load/store
pipeline and
memory access
pipeline.
Contention
FMOV
FCNVSD FPUL,DRn
FCNVDS DRm,FPUL
FMOV.D
FMOV.D
FMOV.D
FMOV.D
FMOV.D
FMOV.D
FMOV.D
FMOV.D
Instructions
DRm,DRn
@Rm,DRn
@Rm+,DRn
@(R0,Rm),DRn
@(disp12,Rm),DRn
DRm,@Rn
DRm,@-Rn
DRm,@ (R0,Rn)
DRm,@(disp12,Rn)

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