R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 50

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
(6) Delayed Branching
With the exception of some instructions, unconditional branch instructions, etc., are executed as
delayed branches. With a delayed branch instruction, the branch is made after execution of the
instruction immediately following the delayed branch instruction. This reduces disruption of the
pipeline when a branch is made.
In a delayed branch, the actual branch operation occurs after execution of the slot instruction.
However, instruction execution for register updating, etc., excluding the branch operation, is
performed in delayed branch instruction → delay slot instruction order. For example, even though
the contents of the register holding the branch destination address are changed in the delay slot,
the branch destination address remains as the register contents prior to the change.
Table 4.2
SH-2A/SH2A-FPU CPU
BRA
ADD
(7) Addition of Unconditional Branch Instructions with No Delay Slot
The SH-2A/SH2A-FPU features the addition of unconditional branch instructions in which a delay
slot instruction is not executed. This makes it possible to cut down on the number of unnecessary
NOP instructions, and so reduce the code size.
(8) Multiplication/Accumulation Operation
16bit × 16bit → 32-bit multiplication operations are executed in one to two cycles. 16bit × 16bit +
64bit → 64-bit multiplication/accumulation operations are executed in two to three cycles. 32bit ×
32bit → 64-bit multiplication and 32bit × 32bit + 64bit → 64-bit multiplication/accumulation
operations are executed in two to four cycles.
(9) T Bit
The T bit in the status register changes according to the result of the comparison, and in turn is the
condition (true/false) that determines if the program will branch. The number of instructions after
T bit in the status register is kept to a minimum to improve the processing speed.
Rev. 3.00 Jul 08, 2005 page 34 of 484
REJ09B0051-0300
TRGET
R1,R0
Delayed Branch Instructions
Description
ADD is executed before
branch to TRGET.
Example of Other CPU
ADD.W
BRA
R1,R0
TRGET