R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 51

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 4.3
SH-2A/SH2A-FPU CPU
CMP/GE R1,R0
BT
BF
ADD
CMP/EQ #0,R0
BT
(10) Immediate Data
Byte immediate data is located in instruction code. Word or longword immediate data is not input
via instruction codes but is stored in a memory table. The memory table is accessed by an
immediate data transfer instruction (MOV) using the PC relative addressing mode with
displacement.
With the SH-2A/SH2A-FPU, immediate data of 17 to 28 bits can be located in an instruction code.
However, for immediate data of 21 to 28 bits, an OR instruction must be executed after a register
transfer.
Table 4.4
Type
8-bit immediate
16-bit immediate
20-bit immediate
28-bit immediate
32-bit immediate
Note: Immediate data is referenced by @(disp,PC).
TRGET0
TRGET1
#–1,R0
TRGET
T Bit
Referencing by Means of Immediate Data
SH-2A/SH2A-FPU CPU
MOV
MOVI20
MOVI20
MOVI20S #H'12345, R0
OR
MOV.L
. . . . . . . . . . .
.DATA.L
Description
T bit is set when R0 ≥ R1. The
program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD. T
bit is set when R0 = 0. The
program branches if R0 = 0.
#H'12,R0
#H'1234, R0
#H'12345, R0
#H'67, R0
@(disp,PC),R0
H'12345678
Rev. 3.00 Jul 08, 2005 page 35 of 484
Example for Other CPU
MOV.W #H'1234,R0
MOV.L
MOV.L
MOV.L
MOV.B
Example for Other CPU
CMP.W R1,R0
BGE
BLT
SUB.W #1,R0
BEQ
Section 4 Instruction Features
#H'12,R0
#H'12345,R0
#H'1234567,R0
#H'12345678,R0
TRGET0
TRGET1
TRGET
REJ09B0051-0300