R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 247

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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6.4.36
Format
MUL.L
Description
Performs 32-bit multiplication of the contents of general registers Rn and Rm, and stores the
bottom 32 bits of the result in the MACL register. The MACH register data does not change.
Operation
Example:
MUL.L(long m,long n)
{
}
MULL R0,R1
STS
MACL=R[n]*R[m];
PC+=2;
Rm,Rn
MACL,R0
MUL.L
Double-Precision
Multiplication
; Before execution: R0 = H'FFFFFFFE, R1 = H'00005555
; After execution:
; Operation result
Abstract
Rn × Rm → MACL
MULtiply Long
/* MUL.L Rm,Rn */
MACL = H'FFFF5556
Code
0000nnnnmmmm0111 2
Rev. 3.00 Jul 08, 2005 page 231 of 484
Section 6 Instruction Descriptions
Arithmetic Instruction
REJ09B0051-0300
Cycle
T Bit

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