R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 496

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix A SH-2A/SH2A-FPU Parallel Execution
MW
MW
ML
MU
ML,MU
SF
FL
ML,FL
FP
Rev. 3.00 Jul 08, 2005 page 480 of 484
REJ09B0051-0300
Instruction
cation of
Classifi-
First
MR
MW
ML
MU
ML
SF
FL
ML,FL
FP
Instruction
cation of
Classifi-
Second
AND.B
BST.B
TAS.B
MOV.B
MOV.B
MOV.B
MOV.W
MOV.W
MOV.L
MOV.L
MOVML.L
STC.L
STS
CLRMAC
MUL.L
LDS
MULR
DIVU
EXTU.B
ROTCR
SHAD
SHLD
SHLL2
SHLR16
SWAP.B
FABS
FLDI1
FMOV
FSTS
STS
FADD
FCMP/GT
FDIV
FLOAT
FMUL
FSQRT
FTRC
#imm,@(R0,GBR)
#imm3,@(disp12,Rn) OR.B
@Rn
R0,@(disp,GBR)
Rm,@Rn
Rm,@(disp12,Rn)
Rm,@(R0,Rn)
R0,@Rn+
Rm,@(disp,Rn)
Rm,@-Rn
Rm,@-R15
VBR,@-Rn
MACH,Rn
Rm,Rn
Rm,MACL
R0,Rn
R0,Rn
Rm,Rn
Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rm,Rn
DRn
FRn
FRm,FRn
FPUL,FRn
FPUL,Rn
DRm,DRn
FRm,FRn
DRm,DRn
FPUL,FRn
FRm,FRn
FRn
DRm,FPUL
BCLR.B
XOR.B
MOV.B
MOV.B
MOV.W
MOV.W
MOV.W
MOV.L
MOV.L
MOVMU.L
STS.L
STS
DMULS.L
MULS.W
LDS
EXTS.B
EXTU.W
ROTL
SHAL
SHLL
SHLL8
SHLR2
SWAP.W
FABS
FLDS
FNEG
FADD
FCNVDS
FDIV
FMAC
FSCHG
FSUB
FTRC
Instruction
#imm3,@(disp12,Rn) BSET.B
#imm,@(R0,GBR)
#imm,@(R0,GBR)
R0,@(disp,Rn)
Rm,@-Rn
R0,@(disp,GBR)
Rm,@Rn
Rm,@(disp12,Rn)
Rm,@(R0,Rn)
R0,@Rn+
Rm,@-R15
PR,@-Rn
MACL,Rn
Rm,Rn
Rm,Rn
Rm,MACH
Rm,Rn
Rm,Rn
Rn
Rn
Rn
Rn
Rn
Rm,Rn
FRn
FRm,FPUL
DRn
FRm,FRn
DRm,FPUL
FRm,FRn
FR0,FRm,FRn
DRm,DRn
FRm,FPUL
STC.L
MOV.B
MOV.B
MOV.W
MOV.W
MOV.L
MOV.L
MOV.L
STC.L
DMULU.L
MULU.W
EXTS.W
ROTCL
ROTR
SHAR
SHLL16
SHLR
SHLR8
XTRCT
FLDI0
FMOV
FNEG
FCMP/EQ
FCNVSD
FLOAT
FMUL
FSQRT
FSUB
#imm3,@(disp12,Rn)
SR,@-Rn
Rm,@(R0,Rn)
R0,@Rn+
R0,@(disp,Rn)
Rm,@-Rn
R0,@(disp,GBR)
Rm,@Rn
Rm,@(disp12,Rn)
GBR,@-Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rn
Rn
Rn
Rn
Rm,Rn
FRn
DRm,DRn
FRn
FRm,FRn
FPUL,DRn
FPUL,DRn
DRm,DRn
DRn
FRm,FRn