R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 359

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Instructions that transfer data from the FPU to the CPU do not conflict with memory access
instructions (figure 8.10). In addition, instructions that transfer data from the CPU to the FPU do
not conflict with memory access instructions (figure 8.11).
(2) When the preceding instruction and succeeding instruction are both instructions that use the
STS
MOV.L R1,@R3
Note: No contention between STS instruction and memory access instruction
LDS
MOV.L @R1+,R3
Note: No contention between LDS instruction and memory read instruction
MULS.W R2,R1
MULR
Multiplier locked
LDS.L @R1+, MACH
MULR R0,R3
multiplier (figure 8.12).
With the multiplier, contention also occurs when a previously issued instruction is locked
(figure 8.13).
In addition, instructions that read MACH or MACL, MULR instructions, and instructions that
transfer the value of FPUL or FPSCR to the CPU cause contention because they share the read
bus (figure 8.14).
FPUL,R0
R0,FPUL
Figure 8.13 Example of Contention Due to Previously Issued Instruction
Figure 8.11 Example of LDS Instruction and Memory Read Instruction
Figure 8.10 Example of Contention between STS and Memory Access
R0,R3
Figure 8.12 Example of Multiplier Contention
IF
IF
IF
IF
IF
IF
IF
IF
IF
IF
ID
DF
ID
ID
DF
ID
ID
—
ID
—
EX
EX
EX
EX
EX
EX
mm
ID
↔
EX
—
WB
NA
MA
NA
MA
mm
mm
MA
ID
SF
WB
SF
WB
mm
WB
mm
Rev. 3.00 Jul 08, 2005 page 343 of 484
WB
mm
mm
: CPU pipeline
: FPU pipeline
: CPU pipeline
: CPU pipeline
: FPU pipeline
: CPU pipeline
WB
Section 8 Pipeline Operation
mm
WA
REJ09B0051-0300