R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 376

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
8.7
Multiply instructions, multiply-and-accumulate instructions, and instructions that manipulate the
registers for these instructions (MACH, MACL) use the multiplier. In addition, the STS FPUL,Rn,
and STS FPSCR,Rn instructions use the multiplication result read bus. Details of pipelining and
contention are given below, with instructions divided into the categories shown. The numbers
immediately following the instructions, in the form (A/B/C), indicate (number of execution
slots/latency/number of lock slots).
• Multiply-and-accumulate instructions
• Multiply instructions (I)
• Multiply instructions (II) (register return)
• Register write instructions (I)
• Register write instructions (II)
• Register read instructions (including STS FPUL,Rn and STS FPSCR,Rn)
Facts about Contention
Contention arises with multi-cycle instructions in the same way as with general instructions
(figure 8.51). See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction, for details.
The following rules apply to instructions that use the multiplier.
Rev. 3.00 Jul 08, 2005 page 360 of 484
REJ09B0051-0300
MAC.L @R1+,@R2+
MAC.L @R3+,@R4+
Note: MAC.L is an instruction with an execution rate of 4.
MAC.L (4/6/5)
MAC.W (3/5/4)
DMUL.S, DMUL.U, MUL.L (2/3/2)
MULS.W, MULU.W(1/2/1)
MULR (2/4/2)
CLRMAC, LDS (1/2/1)
LDS.L (1/3/2)
STS (1/2/0)
STS.L (1/2/0)
Contention Due to Multiplier
Figure 8.51 Example of Multi-Cycle Instructions Using Multiplier
IF
IF
ID
—
EX
—
IF
IF
IF
IF
IF
IF
IF
IF
IF
MA
—
ID
ID
ID
ID
ID
ID
ID
ID
ID
MA
ID
EX
EX
mm mm mm
mm mm
mm mm mm WB
mm mm
EX
EX
EX
mm
EX
MA MA mm mm mm
MA MA mm mm
MA WB
WB
MA
mm
MA
mm
MA
mm
mm
mm