R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 5

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Item
1.1 Features
2.2.2 Control
Registers
(1) Status Register,
SR
3.1.1 Exception
Handling Types and
Priority
Table 3.1 Exception
Types and Priority
3.1.2 Exception
Handling Operation
(2) Address Error,
RAM Error, Register
Bank Error, Interrupt,
or Instruction
Exception Handling
3.3.1 Address Error
Sources
Table 3.5 Bus
Cycles and Address
Errors
3.6.3 Interrupt
Exception Handling
Page
1
5
16
18
22
26
Main Revisions for this Edition
Revision (See Manual for Details)
Description amended
The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set
computer) microprocessor that is upward-compatible with the SH-
1, SH-2, and SH-2E at the object code level.
Description amended
(32-bit,
00XX)
Note amended
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR,
RTS, RTE,
Description amended
⋅⋅⋅ and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
Table amended
Description amended
⋅⋅⋅ and the vector table address offset of the interrupt exception
handling to be executed,⋅⋅⋅
Type
Data
read/write
Bus Cycle
CPU or
DMAC
Bus Master
initial value =0000 0000 0000 0000 00X0 00XX 1111
Double longword data accessed from double
longword boundary
Double longword data accessed from other
than double longword boundary
Bus Cycle Operation
BF/S, BT/S, BSRF, BRAF
Rev. 3.00 Jul 08, 2005 page iii of xiv
Address Error
Occurrence
No error (normal)
Address error
.