R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 241

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.33
Format
MOV.B
MOV.W R0,@(disp,Rn)
MOV.L
MOV.B
MOV.W @(disp,Rm),R0
MOV.L
Description
Transfers the source operand to the destination. This instruction is optimum for accessing data in a
structure or a stack. The data can be a byte, word, or longword, but when a byte or word is
selected, only the R0 register can be used. When the data is a byte, the only change made is to
zero-extend the 4-bit displacement. Consequently, an address within +15 bytes can be specified.
When the data is a word, the 4-bit displacement is zero-extended and doubled. Consequently, an
address within +30 bytes can be specified. When the data is a longword, the 4-bit displacement is
zero-extended and quadrupled. Consequently, an address within +60 bytes can be specified. If the
displacement is too short to reach the memory operand, the aforementioned @(R0,Rn) mode must
be used. When the source operand is in memory, the loaded data is stored in the register after it is
sign-extended to a longword.
Note
When byte or word data is loaded, the destination register is always R0. R0 cannot be accessed by
the next instruction until the load instruction is finished. The instruction order in figure 6.2 will
give better results.
For the Renesas Technology SuperH RISC engine assembler, declarations should use scaled
values (×1, ×2, ×4) as displacement values.
R0,@(disp,Rn)
Rm,@(disp,Rn)
@(disp,Rm),R0
@(disp,Rm),Rn
MOV
Structure Data
Transfer
MOV.B
AND
ADD
Abstract
R0 → (disp + Rn)
R0 → (disp × 2 + Rn)
Rm → (disp × 4 + Rn)
(disp + Rm) → sign extension → R0
(disp × 2 + Rm) → sign extension → R0
disp × 4 + Rm) → Rn
@(2, R1), R0
#80, R0
#20, R1
MOVe structure data
Figure 6.2 Using R0 after MOV
MOV.B
ADD
AND
Rev. 3.00 Jul 08, 2005 page 225 of 484
Code
10000000nnnndddd
10000001nnnndddd
0001nnnnmmmmdddd
10000100mmmmdddd
10000101mmmmdddd
0101nnnnmmmmdddd
Section 6 Instruction Descriptions
@(2, R1), R0
#20, R1
#80, R0
Data Transfer Instruction
REJ09B0051-0300
Cycle
1
1
1
1
1
1
T Bit
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