R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 400

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
(6) Memory Load Instructions (MOVMU.L, MOVML.L)
Instruction Types
Pipeline
Operation
These instructions perform restoration from the stack. The pipeline is in the form IF, ID, EX, MA,
MA, MA, ... MA, WB, with MA repeated as often as necessary. Contention may occur if an
instruction that uses the destination register of this instruction is located within the 3 instructions
following this instruction. (See section 8.5, Effect of Memory Load Instruction on Pipeline.)
Instruction Issuance
If there is an uncompleted instruction in the pipeline when these instructions are decoded,
execution of these instructions will be delayed.
These instructions use the memory access pipeline.
Parallel Execution Capability
These are multi-cycle instructions, and cannot be executed in parallel with a subsequent
instruction. (See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 384 of 484
REJ09B0051-0300
Instruction A
Next instruction
Instruction after next
MOVMU.L
MOVML.L
@R15+,Rn
@R15+,Rn
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
ID
—
IF
EX
—
—
MA
—
—
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⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
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MA
ID
—
MA
EX
ID
MA
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
EX
WB
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