R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 179

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.5
Format
BF
Description
Reads the T bit, and conditionally branches. If T = 0, it branches to the branch destination address.
If T = 1, BF executes the next instruction. The branch destination is an address specified by PC +
displacement. However, in this case it is used for address calculation. The PC is the address 4
bytes after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently,
the relative interval from the branch destination is –256 to +254 bytes. If the displacement is too
short to reach the branch destination, use BF with the BRA instruction or the like.
Note
When branching, three cycles; when not branching, one cycle.
Operation
BF(long d)
{
}
label
long disp;
if ((d&0x80)==0) disp=(0x000000FF & (long)d);
else disp=(0xFFFFFF00 | (long)d);
if (T==0) PC=PC+(disp<<1);
else PC+=2;
BF
Conditional Branch
Abstract
When T = 0, disp × 2 + PC → PC;
When T = 1, nop
/* BF disp */
Branch if False
Code
10001011dddddddd
Rev. 3.00 Jul 08, 2005 page 163 of 484
Section 6 Instruction Descriptions
Branch Instruction
REJ09B0051-0300
Cycle
3/1
T Bit
—