R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 342

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Register Banks
7.2
7.2.1
The contents of general registers R0 to R14, the global register (GBR), the multiply and
accumulate registers (MACH, MACL), the procedure register (PR), and the interrupt vector table
address offsets (VTO) are banked.
7.2.2
The number of register banks is N, numbered from bank 0 to bank N – 1 (maximum 512 banks).
Register banks are stacked in first in last out (FILO) sequence. Saves take place in order,
beginning from bank 0, and retrieves take place in the reverse order, beginning from the last bank
saved to. The number of banks, N, differs depending on the product. For details, refer to the
Register Banks section of the hardware manual for the product in question.
7.2.3
(1) Bank Control Register (IBCR) (16 bit, Initial value: H'0000)
This register is used to allow or prohibit the use of specific register banks, based on the interrupt
priority level or the interrupt source. The register specifications and initial values differ depending
on the product. For details, refer to the Interrupt Controller section of the hardware manual for the
product in question.
Bits 15 to 1: E15 to E1
The setting of these bits is used to allow or prohibit use of register banks based on interrupt
priority level (15 to 1).
Bit 0: Reserved Bit
This bit is always read as 0 and only a value of 0 should be written to it.
Rev. 3.00 Jul 08, 2005 page 326 of 484
REJ09B0051-0300
Bits 15 to 1
E15 to E1
0
1
Bit
E15
15
Register Banks and Bank Control Registers
Banked Data
Register Banks
Bank Control Registers
E14
14
E13
13
Description
Register bank use is prohibited.
Register bank use is allowed.
E12
12
E11
11
E10
10
E9
9
E8
8
E7
7
E6
6
E5
5
E4
4
E3
3
E2
2
E1
1
—
0