R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 462

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
(3) Illegal Instruction Exception Handling
Instruction Type
Illegal instruction exception handling
Pipeline
Operation
An illegal instruction is accepted in the ID stage of an instruction, and processing from that ID
stage onward is replaced by the illegal instruction exception handling sequence. The pipeline ends
after seven stages: IF, ID, EX, EX, MA, MA, MA. Illegal instruction exception handling is not a
delayed branch.
Address error generation sources comprise those related to general illegal instructions and those
related to slot illegal instructions. When undefined code located other than in the slot immediately
after a delayed branch instruction (called the delay slot) is decoded, general illegal instruction
exception handling is performed. When undefined core located in the delay slot is decoded, or an
instruction that modifies the program counter, and a 32-bit instruction, and a RESBANK
instruction, and a DIVU or DIVS instruction are located in the delay slot and decoded, slot illegal
instruction handling is performed.
General illegal instruction exception handling is also performed if an FPU instruction or FPU-
related CPU instruction is executed while the FPU is in the module stopped state.
The IF stage of the branch destination instruction is started from the slot containing the last MA
stage of the illegal instruction exception handling.
Rev. 3.00 Jul 08, 2005 page 446 of 484
REJ09B0051-0300
Illegal instruction
Next instruction
Instruction after next
Branch destination
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
ID
—
IF
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
—
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
MA
MA
MA
IF
ID