R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 454

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
(13) RESBANK Instruction
Instruction Type
Pipeline
• When B0 == 0
• When B0 == 1
Operation
The operation is different when the BO bit is 0 and when the BO bit is 1.
When the BO bit is 0, restoration from a bank is performed. The pipeline comprises IF and ID
followed by EX, EX, EX, EX, EX, EX, EX (nine repetitions of EX), and ends after 11 stages.
During this time, register restoration from the bank is performed.
When the BO bit is 1, restoration from the stack is performed. The pipeline comprises IF, ID, and
EX, followed by MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA,
MA, MA, MA, MA, (19 repetitions of MA), followed by WB, and ends after 23 stages.
Instruction Issuance
When the BO bit is 0, this instruction does not cause resource contention.
When the BO bit is 1, this instruction uses the memory access pipeline.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
(See section 8.3.4, Details of Contention Due to Multi-Cycle Instruction.)
Rev. 3.00 Jul 08, 2005 page 438 of 484
REJ09B0051-0300
Instruction A
Next instruction
Instruction A
Next instruction
RESBANK
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
↔ ↔ ↔ ↔ ↔ ↔ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
IF
IF
IF
IF
ID
—
ID
—
EX
EX
—
—
MA
EX
—
—
MA
EX
—
—
MA
EX
—
—
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
—
↔ ↔ ↔ Slots
MA
EX
—
ID
MA
EX
EX
—
MA
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
ID
WB
EX
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅