R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 134

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.3.16
Format
JSR/N @Rm
JSR/N @@(disp8, TBR)
Description
Branches to a subroutine procedure at the designated address. The contents of PC are stored in PR
and execution branches to the address indicated by the contents of general register Rm as 32-bit
data or to the address read from memory address (disp × 4 + TBR). The stored contents of PC
indicate the starting address of the second instruction after the present instruction. This instruction
is used with RTS as a subroutine procedure call.
Notes
This is not a delayed branch instruction.
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×4) as displacement values.
Rev. 3.00 Jul 08, 2005 page 118 of 484
REJ09B0051-0300
JSR/N
Branch to Subroutine Procedure with No Delay Slot
Abstract
PC - 2→ PR, Rm → PC
PC - 2 → PR, (disp×4+TBR) → PC
Jump to SubRoutine with No delay slot
Code
0100mmmm01001011
10000011dddddddd
Branch Instruction
SH-2A/SH2A-FPU (New)
Cycle
3
5
T Bit
―
―