R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 371

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

When the FPSCR value is read using an STS or STS.L instruction, FPSCR is read after
completion of the previously issued operation. As a result, execution is delayed by an interval of
[latency of preceding operation + 1 slot] (figure 8.41).
Double-precision floating-point arithmetic operation instructions (FADD, FSUB, FMUL) require
6 cycles for the E1 stage. Another floating-point arithmetic operation instruction will not enter the
E1 stage during this interval. If another floating-point arithmetic operation instruction appears
before a double-precision floating-point arithmetic operation instruction finishes the E1 stage, that
floating-point arithmetic operation instruction has its execution delayed by a predetermined slot
interval, and enters the E1 stage after the double-precision floating-point arithmetic operation
instruction has finished the E1 stage. A floating-point load/store instruction arriving during this
interval can be executed (figure 8.42).
With an FDIV or FSQRT instruction, after the E1 stage is used in initialization, operation is
performed by an independent computer (ED stage), after which the operation result is written
back. A floating-point arithmetic operation instruction following either of these instructions
operates as described below. See section 8.9, Pipeline Operations for Each Instruction, for the
kind of pipeline used with each instruction.
(1) During E1 stage use in initialization, another floating-point arithmetic operation instruction
(2) After an FDIV or FSQRT instruction has progressed to the ED stage, an FPU instruction is
Instruction 1 (single-precision)
(FADD FR6,FR9)
Instruction 2
(STS FPSCR,R3)
FADD DR4,DR6
FABS DR0
STS
FMUL DR2,DR0
will not enter the E1 stage. Other instructions enter the E1 stage after FDIV or FSQRT
initialization ends.
executed without delay unless it uses the FDIV or FSQRT instruction result register (figure
8.40).
Figure 8.42 Example of Double-Precision FPU Operation and Next FPU Instruction
FPUL,R0
IF
IF
Figure 8.41 Example of Reading FPSCR
DF
DF
IF
IF
IF
E1
EX
DF
—
DF
IF
E1
NA
EX
—
E1
—
E1
SF
NA
—
E2
—
E1
—
Rev. 3.00 Jul 08, 2005 page 355 of 484
SF
—
E1
—
DF
E1
DF
Section 8 Pipeline Operation
EX
E2
E1
REJ09B0051-0300
NA
SF
E2
SF
SF