R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 446

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
(b) When a CLRMAC instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
(c) When a CLRMAC instruction is immediately followed by an LDS.L (memory) instruction
Instruction Issuance
These instructions use the multiplier.
These instructions lock the multiplier for a 1-slot interval.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 430 of 484
REJ09B0051-0300
CLRMAC
STS MACL,Rn
Instruction after next
CLRMAC
LDS.L @Rn+,MACL
Instruction after next
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
Parallel execution with the CLRMAC instruction is not possible, as it locks the multiplier.
Execution is delayed for a CLRMAC instruction execution state (1-slot) interval.
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
IF
IF
ID
—
ID
—
IF
IF
mm
mm
ID
ID
ID
ID
mm
mm
EX
EX
EX
EX
WB
MA
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
WB