R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 427

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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(7) Memory Bit Operation Instructions
Instruction Types
Pipeline
Operation
The pipeline ends after six stages: IF, ID, EX, MA, EX, MA.
Instruction Issuance
These instructions use the memory access pipeline.
Parallel Execution Capability
These are 32-bit instructions, and cannot be used in parallel execution. (See section 8.3.5, Details
of Contention Due to 32-Bit Instruction.)
Instruction A
Next instruction
Instruction after next
BCLR.B #imm3,@(disp12,Rn)
BSET.B #imm3,@(disp12,Rn)
BST.B
#imm3,@(disp12,Rn)
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
ID
IF
IF
EX
MA
EX
ID
MA
EX
ID
Rev. 3.00 Jul 08, 2005 page 411 of 484
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EX
Section 8 Pipeline Operation
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REJ09B0051-0300

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