R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 465

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(2) FPSCR Load Instructions
Instruction Types
Pipeline
Operation
The CPU pipeline ends after four stages – IF, ID, EX, MA – and the FPU pipeline after five stages
– IF, DF, EX, NA, SF. A subsequent FPU-related instruction is stalled for the next 3 cycles.
Instruction Issuance
These instructions use the FPU load/store pipeline.
The LDS.L instruction also uses the memory access pipeline.
If an FPU arithmetic operation instruction is still performing calculation, these instructions are
kept waiting until that instruction ends.
Parallel Execution Capability
These instructions cannot be executed in parallel with FPU instructions or FPU-related CPU
instructions.
Instruction A
Next instruction
Instruction after next
LDS
LDS.L
Rm,FPSCR
@Rm+,FPSCR
↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
IF
IF
DF
ID
—
—
IF
IF
EX
EX
DF
DF
ID
ID
MA
NA
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
EX
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
SF
Rev. 3.00 Jul 08, 2005 page 449 of 484
Section 8 Pipeline Operation
: CPU pipeline
: FPU pipeline
: CPU pipeline
: FPU pipeline
: CPU pipeline
: FPU pipeline
REJ09B0051-0300