R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 284

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.4.64
Format
TAS.B @Rn
Description
Reads byte data from the address specified by general register Rn, and sets the T bit to 1 if the data
is 0, or clears the T bit to 0 if the data is not 0. Then, data bit 7 is set to 1, and the data is written to
the address specified by Rn. During this operation, the bus is not released.
Operation
Example:
Rev. 3.00 Jul 08, 2005 page 268 of 484
REJ09B0051-0300
TAS(long n)
{
}
_LOOP TAS.B @R7
long temp;
temp=(long)Read_Byte(R[n]);
if (temp==0) T=1;
else T=0;
temp|=0x00000080;
Write_Byte(R[n],temp);
PC+=2;
TAS
Memory Test
and Bit Setting
BF
Abstract
When (Rn) is 0, 1 → T, 1 → MSB
of (Rn)
/* TAS.B @Rn */
_LOOP
Test And Set
; R7 = 1000
; Loops until data in address 1000 is 0
0100nnnn00011011 3
Code
/* Bus Lock enable */
/* Bus Lock disable */
Logical Instruction
Cycle
T Bit
Test results